library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Adder_Project_toplevel is
Port(
		A	: in STD_LOGIC_VECTOR(3 downto 0);
		B	: in STD_LOGIC_VECTOR(3 downto 0);
		S	: out STD_LOGIC_VECTOR(3 downto 0);
		C_out : out std_logic;
		C_in0 : in std_logic
		);
end Adder_Project_toplevel;


architecture structural of Adder_Project_toplevel is

signal C_in1      : STD_LOGIC;
signal C_in2      : STD_LOGIC;
signal C_in3      : STD_LOGIC;

    component Adder_Project is
        Port (
			SW1	: in std_logic;
			SW2	: in std_logic;
			S	: out std_logic;
			C_out : out std_logic;
			C_in : in std_logic
        );
    end component;
	
	begin
	 FA1: Adder_Project port map(
        SW1  => A(0),
        SW2   => B(0),
        C_in => C_in0,
		  C_out => C_in1,
		  S => S(0)
    );
	 
	 FA2: Adder_Project port map(
        SW1  => A(1),
        SW2   => B(1),
        C_in => C_in1,
		  C_out => C_in2,
		  S => S(1)
    );
	 
	 FA3: Adder_Project port map(
        SW1  => A(2),
        SW2   => B(2),
        C_in => C_in2,
		  C_out => C_in3,
		  S => S(2)
    );
	 
	 FA4: Adder_Project port map(
        SW1  => A(3),
        SW2   => B(3),
        C_in => C_in3,
		  C_out => C_out,
		  S => S(3)
    );
end structural;