library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Adder_Project is
	Port(
		SW1	: in std_logic;
		SW2	: in std_logic;
		S	: out std_logic;
		C_out : out std_logic;
		C_in : in std_logic
		);
end Adder_Project;

architecture gate_level of Adder_Project is

begin
 
 S <= SW1 XOR SW2 XOR C_in ;
 C_out <= (SW1 AND SW2) OR (C_in AND SW1) OR (C_in AND SW2) ;

end gate_level;