library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity binary_to_bcd_4bit is
    Port (
        bin_in  : in  unsigned(3 downto 0);  -- 4-bit binary input
        bcd_high : out unsigned(3 downto 0); -- Tens digit (0 or 1)
        bcd_low  : out unsigned(3 downto 0)  -- Ones digit (0-9)
    );
end binary_to_bcd_4bit;

architecture Behavioral of binary_to_bcd_4bit is
    signal shift_reg : unsigned(7 downto 0);  -- 4 bits binary + 2 BCD digits
begin
    process(bin_in)
    begin
        -- Initial shift register with 4-bit binary input
        shift_reg := (others => '0');
        shift_reg(3 downto 0) := bin_in;

        -- Shift and add-3 BCD conversion
        for i in 0 to 3 loop
            if shift_reg(7 downto 4) >= "0100" then
                shift_reg(7 downto 4) := shift_reg(7 downto 4) + 3;
            end if;
            shift_reg := shift_reg(6 downto 0) & '0'; -- Left shift
        end loop;

        -- Output the BCD digits
        bcd_high <= shift_reg(7 downto 4);  -- Tens place
        bcd_low  <= shift_reg(3 downto 0);  -- Ones place
    end process;
end Behavioral;